1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method for forming CMOS integrated circuit gate conductors having reduced susceptibility to polysilicon depletion and boron penetration.
2. Description of the Related Art
Fabrication of a metal oxide semiconductor field-effect transistor ("MOSFET") device is well known. MOSFETs are generally manufactured by placing an undoped polycrystalline silicon ("polysilicon") layer over a relatively thin silicon dioxide ("oxide") layer. The polysilicon layer and the oxide layer are then patterned to form a gate conductor arranged upon a gate oxide with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor may be used to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The gate conductor and source/drain regions are then concurrently implanted with a dopant species. If the dopant species used is n-type, then the resulting MOSFET is an NMOS ("n-channel") transistor device. Conversely, if the dopant species is p-type, then the resulting MOSFET is a PMOS ("p-channel") transistor device. Integrated circuits typically use either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. The combination of an n-channel device and a p-channel device on a single substrate is termed a complementary MOS ("CMOS") device.
CMOS circuits offer numerous performance, reliability, design, and cost advantages over NMOS or PMOS circuits, and have become the dominant integrated circuit technology. One basic process for forming transistors for CMOS circuits (hereinafter "the basic CMOS process") only requires slight modification of the general technique for forming MOSFETs described above. In the basic CMOS process, a thin oxide layer is first formed upon a silicon substrate. The silicon substrate contains two active regions laterally separated by a field region. The field region includes an isolation structure, which may be formed by trench isolation or local oxidation of silicon ("LOCOS") techniques. A single layer of undoped polysilicon is then deposited on the oxide layer. Gate structures are then formed within the active regions by patterning the layer of polysilicon and the layer of oxide. The resulting structures each include a gate conductor formed from the polysilicon layer and a gate oxide formed from the oxide layer. One of the active regions, typically the region in which the p-channel device is to be formed, is covered with a masking layer of photoresist. N-type dopants are concurrently implanted into the other gate conductor and the adjacent semiconductor substrate. Such implantation serves both to dope the gate conductor and to form lightly-doped regions ("LDD") in the silicon substrate. Oxide spacers are then formed on the sidewall of the uncovered gate structure. A second implant dose is then forwarded into the gate structure and the silicon substrate adjacent to the exposed lateral surfaces of the spacers. The second implant is done at a higher implant energy and dose than the first and creates source/drain regions within the silicon substrate. The process is then repeated for the p-channel transistor, except now p-type dopants are implanted.
As implied above, ion implantation is commonly used both for forming junctions and for doping the gate conductor. An advantage of ion implantation over older techniques such as solid-state diffusion is that ion implantation allows greater control over the dopant profile. By modifying the implant dose and energy appropriately, the depth of the implanted area and the dopant distribution within that area may be precisely controlled. Because of this property, ion implantation is usually used to form the shallow junctions necessitated by the sub-micron channel lengths common in MOS transistors. Shallow junctions help reduce susceptibility to short-channel effects, make the device less prone to punchthrough effects, and reduce parasitic capacitance. By reducing the vertical depth of the junctions, the lateral spread of dopants beneath the gate structure from these regions is also curtailed. Hence, the degree of reduction in effective channel length resulting from dopant migration is lessened. To achieve shallow junctions, relatively low implant energies are used to ensure that the dopants are implanted close to the upper surface of the semiconductor substrate.
In forming MOS devices with polysilicon gate conductors, the polysilicon from which the gate conductor is formed must be doped to lower its sheet resistivity. Dopants should also be implanted sufficiently deep within the gate conductor that a large quantity of the dopants diffuse to the bottom of the gate conductor during subsequent heat processing. Accordingly, dopants, particularly heavier n-type atoms such as arsenic, must be given a relatively high implant energy to ensure that these atoms are implanted sufficiently deep within the gate conductor. On the other hand, dopants that diffuse relatively quickly through polysilicon, such as boron, do not need to be implanted as deeply. Regardless of the diffusion rate through polysilicon of the implanted dopant, the ideal implant energy for doping the gate conductor is often higher than the ideal implant energy for forming shallow junctions. Furthermore, the different diffusion rates through polysilicon for n-type dopants (e.g., arsenic and phosphorus) and p-type dopants (e.g., boron and boron difluoride) may be problematic when attempting to form p-channel and n-channel gate conductors from a single polysilicon layer. Two conditions that can result in such a situation are polysilicon depletion and boron penetration.
Arsenic is typically used to dope the polysilicon gate and to form junctions within the silicon substrate for n-channel devices. As stated above, arsenic is a relatively slow diffuser and will not readily migrate through polysilicon even during substantial heat treatment. If arsenic is not implanted deep into the gate conductor, the arsenic diffusion that will result from subsequent heat processing may not be enough to cause a sufficient quantity of arsenic to migrate near the polysilicon/oxide interface. Thus, a lower portion of the polysilicon remains substantially undoped or "depleted". The undoped lower portion of the gate conductor acts as a high permittivity region that deleteriously hinders performance of the transistor by increasing the effective thickness of the gate oxide. This increase in effective oxide thickness can cause the "turn-off" characteristics of the transistor to increase beyond acceptable values.
Boron, in the form of boron or boron difluoride ions, is typically used to dope the polysilicon gate and to form the junctions within the silicon substrate for p-channel devices. The diffusion rate of boron in polysilicon is relatively high, so boron implanted into a gate conductor will migrate significantly during heat processing. Boron penetration can occur when boron atoms are implanted too deeply into the gate conductor. In such circumstances, the diffusion of these atoms can result in the atoms penetrating the gate oxide. This penetration may reduce the reliability of the gate oxide. Furthermore, boron may even continue through the gate oxide into the underlying channel. The presence of boron in the channel can change the doping concentration in the channel, resulting in threshold voltage shift. Boron penetration into the channel can also cause other undesirable effects such as an increase in electron trapping, a decrease in low-field hole mobility, and degradation of the drive current. Because boron migrating from the lower portions of the gate conductor as a result of uncontrolled channel doping may leave the lower portion of the gate conductor with a less than optimal dopant concentration, boron penetration can also cause polysilicon depletion.
Since the basic CMOS process forms both the n-channel and p-channel gate conductor from the same layer of polysilicon, both gate conductors will have the same thickness. While it may be beneficial to increase the thickness of the gate conductors by increasing the thickness of the polysilicon layer from which they are formed so that boron penetration is minimized, such an increase would make getting the necessary amount of arsenic to the polysilicon-oxide interface in the n-channel conductor even more difficult. Likewise, decreasing the thickness of the polysilicon layer from which the gate conductors are formed would help ensure that arsenic was implanted sufficiently deep in the n-channel conductor, but the reduction in the height of the p-channel gate conductor may increase the probability of boron penetration in that device.
One prior process that attempts to resolve this dilemma starts by depositing a single layer of polysilicon upon an oxide layer. The oxide layer overlies a pair of active areas within a silicon substrate. A mask is formed over the portions of the polysilicon layer above the active area in which the n-channel device will be fabricated, and the uncovered portions of the polysilicon layer are implanted with a p-type dopant such as boron. The previously implanted portions of the polysilicon layer are now covered with a mask while the undoped portion of polysilicon layer overlying the n-channel active area is etched back to a second thickness that is substantially less than the initial thickness of the polysilicon layer. An n-type dopant such as arsenic is then implanted into the unmasked portions of the polysilicon layer. The polysilicon layer is then patterned to produce a relatively thick p-doped gate conductor in one active area and a thinner n-doped gate conductor in the other active area. In this manner, the p-doped gate conductor may be made thick enough to prevent boron penetration and the n-doped gate conductor may be thin enough to ensure that an adequate amount of n-type dopant is placed at the gate conductor lower elevations.
Unfortunately, the above-described process has numerous disadvantages. One of these disadvantages arises from the fact that it is difficult to achieve highly accurate thickness control when etching back a layer of polysilicon. If the precise thickness of the n-channel gate conductor is not known, correctly modeling device properties may be difficult. In addition, a layer of photoresist will be spun on and developed to define the pattern for subsequent etching of the p-channel gate conductor and n-channel gate conductor. The difference between the thickness of the polysilicon layer at the portion from which the p-channel conductor will be formed and the thickness of the polysilicon at the portion from which the n-channel gate conductor will be formed can unfortunately lead to, for example, depth of field problems when exposing the photoresist. This and other focus problems may lead to an inaccurate pattern being transferred to the resist, and ultimately to the polysilicon layer. Furthermore, it is preferred that etching of the polysilicon layer to form each gate conductor occurs concurrently. The polysilicon layer is thicker, however, in the portions from which the p-channel device will be formed than in the portions from which the n-channel device will be formed. Consequently, a simultaneous etch of both of these portions will reach the portions of the oxide layer beneath the portions of the polysilicon layer earlier on the n-doped side of the polysilicon layer than on the p-doped side. The gate conductor etch process must, unfortunately, be made more complex to resolve this situation.
Therefore, it would be desirable to develop a technique for fabricating adjacent n-channel and p-channel transistors that have gate conductors of similar heights but are still substantially resistant to polysilicon depletion and boron migration. It would be further beneficial to achieve such goals without needing to rely on etchback techniques to control the thickness of the gate conductors. The process should allow dopant implantation of the gate conductors to be carried out independently of dopant implantation for junction formation.